† Corresponding author. E-mail:
Project supported by the Beijing Municipal Natural Science Foundation, China (Grant No. 4162030) and the National Science and Technology Major Project of China (Grant No. 2013ZX02303002).
The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing (TLP) test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal–oxide–semiconductor (CMOS) process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.
Electrostatic discharge (ESD) remains a reliability issue in semiconductor industry with the critical dimension scaling down.[1,2] In order to meet the tighter requirements in advanced complementary metal–oxide–semiconductor (CMOS) process, the diode-triggered silicon controlled rectifier (DTSCR) device is widely used due to its design simplification and adjustable trigger/holding voltage. Besides, the extremely low parasitic capacitance makes the DTSCR more popular in high frequency applications with less influence on signal integrity.[3–8] The ESD behaviors of the conventional DTSCR structure are extensively investigated with the transmission line pulsing (TLP) test and device simulation.[9–14] Considering the structure-dependent characteristics, the analysis combined with an equivalent mathematic model is still needed.
In this paper, a kind of mathematical analysis model is presented to explore this problem in conjunction with device simulations. The relevant devices are verified in a 65-nm CMOS process and the test results are in good agreement with the theoretical discussions. In Section 2, TLP test results of the conventional DTSCR structure are provided and device simulations are used to explore operating mechanism. According to the physical process analyzed, the structure-sensitive mathematical model is established to investigate ESD behaviors in Section 3. On the basis of the proposed model, the performances of the novel device configuration are predicted and confirmed by the TLP test results shown in Section 4. Finally, the conclusions are reached in Section 5.
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TLP system is used to produce as short as 100-ns pulses to investigate the ESD behaviors of the device under test. The critical characteristics can be observed in the I–V curve, such as the trigger current, holding current, the secondary breakdown current, etc.
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![]() | Fig. 2. Comparison of I–V behavior between experimental and simulated results of the conventional DTSCR with a width of 80 μm. |
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The mathematical model of the conventional DTSCR is established to explore the influence of structure-dependent parasitic resistance on current division in the substrate, which was mentioned in Section 2. Compared with the model in previous research, the proposed mathematical model takes the parasitic SCR resistance into consideration. In addition, the influences of the critical parameters on the parasitic SCR resistance are also discussed. The cross-section and its equivalent circuit of the proposed model are depicted in Figs.
![]() | Fig. 4. Mathematical analysis model in (a) cross-section and (b) equivalent circuit of the conventional DTSCR. |
It is assumed that each diode cut-in voltage is identical, and R0 is the parasitic resistance between adjacent N-wells on the condition that the conducting current is Iy0. If the transport current is changed into αIy0(α > 0), then the equivalent resistance will be R0/α based on Ohm’s law. Under these assumptions, Ry can be expressed as
As mentioned above, R0 is proportional to the space between the neighboring N-wells, and it will be K × R0 if the space is changed, where K is a constant, K > 1 if the space is extended and K < 1 if it is shortened.
From structures (a) to (e), Rx remains the same and Ry is regularly increased on the basis of math model analysis. Considering the extremely low resistivity in metal, the value of Rz keeps constant. That is to say, only the Ry is structure-sensitive in this situation. The Related device simulations are well performed to confirm the principle of dynamic variation of the parasitic resistance before the intrinsic SCR is triggered on. A current pulse of 0.6 mA/μm is used to investigate the current paths in these structures and the simulated current density of each device is depicted in Fig.
![]() | Fig. 5. Total current densities at 100 ns when the intrinsic SCR is at blocked state under the pulse of 0.6 mA/μm. |
The three similar current routes are observed among these structures. Meanwhile, the distinctions cannot be ignored in the contour lines of current density. It can be concluded that changes of the structure have no influence on the ESD-related physical process, but have an effect on the total current division in the mentioned three paths. This qualitatively validates the discussion in the proposed math model. For a more in-depth insight into this phenomenon, a quantitative relation is still needed. Therefore, terminal currents of the conventional DTSCR structure (a) are extracted and depicted in Fig.
![]() | Fig. 6. Curves of simulated terminal current versus time, which are extracted from DTSCR structure (a) under a pulse of 0.6 mA/μm. |
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![]() | Fig. 7. Curves of simulated terminal current versus time, which change with the device structure under a pulse of 0.6 mA/μm. |
In Fig.
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![]() | Fig. 9. Total current density distributions at 100 ns when the intrinsic SCR is at a latched state under a pulse of 20 mA/μm. |
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The tested DTSCR structures are fabricated in a 65-nm CMOS process. The widths of all devices are selected to be 80 μm. Compared with the normal space 1.5 μm between adjacent N-wells, the mentioned large space is set to be 6×1.5 μm. Figure
The turn-on processes of the DTSCR structures under ESD stress are investigated in detail. Compared with the device simulation, a mathematical model is proposed to get a more in-depth insight into the structure-dependent TLP characteristics. This proposed mathematical model can be smoothly applied to other technologies. With a large space inserted into the coupled diodes, the novel DTSCRs are constructed and taped out in a 65-nm CMOS process. On the basis of the model analysis, the prediction of the related ESD behaviors is provided and finally verified by the device simulations and TLP test results. The detailed discussion may offer an effective instruction when the DTSCR-based ESD protection is needed. Meanwhile, the method is also presented to solve the problem about the tradeoff between the leakage and trigger voltage in DTSCRs, the space and inserted position can be flexibly adjusted to satisfy different I/O requirements.
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